The present invention relates to a liquid crystal display device in which a plurality of pixel electrodes are partitioned by wiring lines.
In recent years, developments have been actively made to attain a technique of providing a liquid crystal display device having a large screen in which a number of display pixels are arrayed at a high density and which can display a quality image at a high resolution. In particular, active matrix liquid crystal display devices attract a public attention on the grounds that they can display a high-contrast image on a large light-transmission screen, while reducing crosstalk between adjacent pixels. As a result, remarkable progress is observed in the art as compared with that of different types of liquid crystal display devices.
The active matrix liquid crystal display device generally comprises an array substrate which includes a matrix array of pixel electrodes; scanning lines formed along the rows of the pixel electrodes; signal lines formed along the columns of the pixel electrodes; and thin film transistors (TFTs) formed near intersections between the scanning lines and the signal lines and each serving as a switching element for applying a drive voltage supplied through a corresponding signal line to a corresponding pixel electrode in response to a selection via a corresponding scanning line. Each pixel electrode is located along with the corresponding TFT in a region defined by the scanning line and the signal line.
The image quality of the liquid crystal display device is liable to be influenced by a parasitic capacitance corresponding to a capacitive coupling between the signal line and the pixel electrode. Such an influence can be suppressed by using, for example, a storage capacitance line or shield electrode set at a predetermined potential and capacitively coupled to the pixel electrode and the signal line.
However, the use of a storage capacitance line or shield electrodes causes the following problems. The storage capacitance line must be large in size to obtain a capacitance which sufficiently suppresses the influence caused due to the parasitic capacitance described above. The large-sized storage capacitance line decreases the aperture ratio of each pixel. Further, since each pixel electrode is located between two signal lines, two shield electrodes are symmetrically arranged to overlap the signal lines with minimum overlapped areas which do not considerably increase the capacitive loads of the signal lines. In this structure, it is necessary that two shield electrodes on both sides of each signal line be separated from each other by a distance substantially equal to the minimum wiring gap Dmin, as shown in FIG. 2. This decreases the aperture ratio of each pixel.